Semiconductor products are included, for instance, flash memory products comprising a plurality of memory cells like NROM (nitride read only memory) or alternative kinds of non-volatile memory cells like floating gate cells. In a flash memory, the memory cells are programmable individually selectively to the respective other memory cells. When information is deleted, all memory cells of the same particular sector are commonly deleted at the same time. The memory cells of the respective sector may be later reprogrammed individually.
The memory cells of a flash memory are arranged in a virtual ground array or in other array architectures. Each memory cell is connected to two respective bitlines running parallel to one another. In a virtual ground array each bitline is connected to memory cells arranged on opposed sides of the bitline. Connection between the bitlines and the memory cells is provided by contact structures which comprise first contacts called “local interconnect”. The local interconnects are arranged in rows extending perpendicular to the direction of the bitlines. In direction parallel to the bitlines, a bitline is connected to one respective local interconnect of every other row of local interconnects. Furthermore, in every other row, the local interconnects have a lateral offset relative to the lateral positions of the local interconnects of the other rows of local interconnects. Each bitline is connected to local interconnects of every other row (for instance of a first, third, fifth etc. row) whereas the bitline is passing over memory cells of a second, fourth, sixth etc. row of local interconnects without being connected to the local interconnects of the second, fourth and sixth row.
In a virtual ground array, the bitlines are connected to the memory cells via contact structures which, according to prior art, comprise a first contact called “local interconnect”. The local interconnects are contact hole fillings provided in a dielectric layer above a substrate. The local interconnects are wide via contacts having a main extension in a first lateral direction perpendicular to the direction of the bitlines. They serve to connect two line-shaped active areas, seen from top view on the main surface of the semiconductor substrate, to a bitline. The active areas are doped regions providing the source/drain regions and the channel regions and, in a virtual ground array, are formed in lines or stripes separated from one another by trench insulation fillings like shallow trench isolations (STI). The trench isolation fillings as well as the active areas are formed line-shaped in top view on the semiconductor substrate. When the bitlines are formed, they are positioned such that they are running parallel to the active areas but are located at same lateral positions as the shallow trench isolation fillings, that is, at lateral positions centered between two respective adjacent line-shaped active areas.
The local interconnects contacts, in direction perpendicular to the active areas, extend beyond the bitlines on opposed sides of the respective bitline. In particular, the local interconnects extend to the active areas next to the bitline positioned on opposed sides of the bitline. Typically a local interconnect has a width being three times the width of the bitline since the width of the active areas and the trench isolation fillings between the active areas correspond to one another.
In order to connect the bitline to the local interconnects which are much wider than the bitlines, second contacts (the “contacts to interconnect”) are formed according to prior art. To this end, a second dielectric layer is deposited on the first dielectric layer and via contact holes are etched in the second dielectric layer so as to expose a portion of an upper surface of the local interconnects. The contact holes in the second dielectric layer are then filled with conductive material. By planarizing the conductive material, the contacts to interconnect are formed. Subsequently, according to prior art the bitlines are to be formed in an aligned position relative to the contacts to interconnect. To this end, a conductive layer is deposited on the intermediate semiconductor product and is patterned using lithographic techniques. However, lithographic patterning requires alignment of the lithographic mask for bitline formation in lateral direction relative to the contacts to interconnect. However, there is a risk of misalignments of the bitlines relative to the contacts to interconnect. Furthermore, the formation of the contacts to interconnect bears the risk of structural defects of the contacts to interconnect since the vias in the second dielectric layer have small dimensions in two lateral directions, thereby reducing the process window for lithographic parameters.
Furthermore, in case of misalignment in direction perpendicular to the active areas during bitline etching, there is a risk that two adjacent bitlines are offset such that they both are connected to the same contact to interconnect and are thus short-circuited to one another. In such a case, the bitlines are approximately located at positions at which dielectric material surrounding the bitlines is actually intended to be located. Accordingly, correct alignment of the bitlines relative to the contact to interconnect structures is critical.
In particular in case that, in direction perpendicular to the active areas, the contact holes in the second dielectric layer are significantly offset with respect to the bitline positions, the contact to interconnect structures filling the contact holes are arranged closer to an adjacent bitline. An adjacent bitline, especially in case of additional misalignment of the bitlines, may easily contact the contact to interconnect structure and thereby may be short-circuited to that bitline, which should pass over the contact to interconnect structure in a laterally centered position. Accordingly, the risk of bitline-to-bitline shorts is rather high.